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w9864g2db 512k 4 banks 32 bits sdram publication release date: january 27, 2003 - 1 - revision a1 table of contents- 1. general d escription......................................................................................................... ......... 3 2. features .................................................................................................................... ..................... 3 3. available part num ber....................................................................................................... ....... 3 4. pin conf igurati on ........................................................................................................... ............ 4 5. pin des cription ............................................................................................................. ................ 5 6. block diagram ............................................................................................................... ............... 6 7. functional descript ion...................................................................................................... ...... 7 power up and in itialization.................................................................................................... ............ 7 programming m ode regi ster ...................................................................................................... ...... 7 bank activa te co mmand.......................................................................................................... ......... 7 read and write access modes.................................................................................................... ..... 7 burst read comm and............................................................................................................. .......... 8 burst co mmand .................................................................................................................. .............. 8 read interrupted by a read..................................................................................................... ......... 8 read interrupted by a write .................................................................................................... .......... 8 write interrupt ed by a write ................................................................................................... ........... 8 write interrupt ed by a read .................................................................................................... .......... 8 burst stop comm and ............................................................................................................. ........... 8 addressing sequence of sequential mode....................................................................................... 9 addressing sequence of interleave mode ........................................................................................ 9 auto-prechar ge comm and......................................................................................................... ..... 10 precharge comm and .............................................................................................................. ........ 10 self refres h comm and........................................................................................................... ........ 10 power down mode ................................................................................................................ .......... 10 no operati on comm and ........................................................................................................... ...... 11 deselect comm and............................................................................................................... .......... 11 clock sus pend m ode ............................................................................................................. ......... 11 table of oper ating modes....................................................................................................... ........ 12 simplified st ate di agram ....................................................................................................... .......... 13 8. dc charact eristics .......................................................................................................... ........ 14 absolute maxi mum ra ting ........................................................................................................ ...... 14 recommended dc operat ing condi tions....................................................................................... 14 capacit ance .................................................................................................................... ................ 14
w9864g2db - 2 - dc characte ristics ............................................................................................................. ............. 15 9. ac chara cteris tics .......................................................................................................... ........ 16 10. timing wavefor ms ........................................................................................................... ........ 19 command input timing ........................................................................................................... ........ 19 read ti ming .................................................................................................................... ................ 20 control timing of input data ................................................................................................... ........ 21 control timing of output data .................................................................................................. ...... 22 mode register set cycle ........................................................................................................ ........ 23 11. operating ti ming example................................................................................................... .24 interleaved bank read (burst length = 4, cas latency = 3) ........................................................ 24 interleaved bank read (burst length = 4, cas latency = 3, autoprec harge) .............................. 25 interleaved bank read (burst length = 8, cas latency = 3) ........................................................ 26 interleaved bank read (burst length = 8, cas latency = 3, autoprec harge) .............................. 27 interleaved bank write (burst length = 8)...................................................................................... 28 interleaved bank write (burst length = 8, au toprechar ge) ............................................................ 29 page mode read (burst length = 4, cas lat ency = 3)................................................................. 30 page mode read/write (burst lengt h = 8, cas lat ency = 3) ....................................................... 31 autoprecharge read (burst lengt h = 4, cas lat ency = 3)............................................................ 32 autoprecharge write (burst lengt h = 4) ......................................................................................... 33 autorefres h cycle.............................................................................................................. .............. 34 self-refres h cycle............................................................................................................. ............... 35 bust read and single write (burst length = 4, cas latency = 3)................................................. 36 power-dow n mode ................................................................................................................ .......... 37 auto-precharge timi ng (write cycle)............................................................................................ .. 38 auto-precharge ti ming (read cycle) ............................................................................................. 39 timing chart of read to write cycle............................................................................................ ... 40 timing chart of write to read cycle............................................................................................ ... 41 timing chart of burst stop cy cle (burst st op comm and).............................................................. 42 timing chart of burst stop cycle (prechar ge comm and).............................................................. 43 cke/dqm input timi ng (write cycle)............................................................................................. 44 cke/dqm input timi ng (read cy cle) ............................................................................................ 45 self refresh/power down mode exit timing .................................................................................. 46 12. package di mensio ns ......................................................................................................... ...... 47 tfbga 90 balls pi tch = 0.8 mm .................................................................................................. ... 47 13. version history ............................................................................................................ ........... 48
w9864g2db publication release date: january 27, 2003 - 3 - revision a1 1. general description w9864g2db is a high-speed synchronous dynamic random access memory (sdram), organized as 512k words 4 banks 32 bits. using pipelined architecture and 0.175 m process technology, w9864g2db delivers a data bandwidth of up to 286m bytes per second (-7). w9864g2db -7. accesses to the sdram are bur st oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generat ed by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the sy stem can change burst l ength, latency cycle, interleave or sequential burst to maximize its perfo rmance. w9864g2db is ideal for main memory in high performance applications. 2. features ? 2.7v ? 3.6v power supply ? 524288 words 4 banks 32 bits organization ? self refresh current: standard and low power ? cas latency: 2 and 3 ? burst length: 1, 2, 4, 8, and full page ? sequential and interleave burst ? burst read, single write operation ? byte data controlled by dqm ? power-down mode ? auto-precharge and controlled precharge ? 4k refresh cycles/ 64 ms ? interface: lvttl ? packaged in tfbga 90 balls pitch = 0.8 mm using pb free materials 3. available part number part number speed (cl = 3) self refresh current (max.) W9864G2DB-7 143 mhz 1 ma
w9864g2db - 4 - 4. pin configuration cke a8 a6 dq23 a4 clk a9 a7 a5 we# cas# cs# bs0 a10 a1 a3 dqm0 ras# bs1 a0 a2 1 26 5 7 9 8 4 3 c b a p n g d e m h l f k r j vdd vdd vdd vddq vddq vddq vddq vddq vdd vddq vddq vddq vddq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vddq nc nc nc/a11 nc/a12 nc dqm2 dq21 dq19 dq20 dq22 dq18 dq17 dq16 dq7 dq6 dq5 dq1 dq3 dq4 dq0 dq2 vss vss vss vss dqm3 dqm1 dq26 dq24 dq28 dq27 dq25 dq29 dq30 dq31 dq15 dq13 dq11 dq12 dq14 dq10 dq9 dq8 nc nc top view
w9864g2db publication release date: january 27, 2003 - 5 - revision a1 5. pin description ball location pin name function description g1 ? g3, g7 ? g9, f7, f3, h1, h2, j3 a0 ? a10 address multiplexed pins for row and column address. row address: a0 ? a10. column address: a0 ? a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. j7, h8 bs0, bs1 bank select select bank to activate duri ng row address latch time, or bank to read/write during address latch time. a1, a2, a8, a9, b1, b9, c2, c3, c7, c8, d2, d3, d7, d8, e2, e8, l2, l8, m2, m3, m7, m8, n2, n3, n7, n8, p1, p9, r1, r2, r8, r9 dq0 ? dq31 data input/ output multiplexed pins for data output and input. j8 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. j9 ras row address strobe command input. when sampled at the rising edge of the clock ras , cas and we define the operation to be executed. k7 cas column address strobe referred to ras k8 we write enable referred to ras k9, k1, f8, f2 dqm0 ? 3 input/output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. j1 clk clock inputs system clock used to sample inputs on the rising edge of clock. j2 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. a7, f9, l7, r7 v dd power (+3.3v) power for input buffers and logic circuit inside dram. a3, f1, l3, r3 v ss ground ground for input buffers and logic circuit inside dram. b2, b7, c9, d9, e1, l1, m9, n9, p2, v dd q power (+3.3v) for i/o buffer separated power from v dd , to improve dq noise immunity. b8, b3, c1, d1, e9, l9, m1, n1, p8, v ss q ground for i/o buffer separated ground from v ss , to improve dq noise immunity. e3, e7, h3, h7, h9, k2, k3 nc no connection no connection
w9864g2db - 6 - 6. block diagram dq0 dq31 dqm0~3 clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 2048 * 256 * 32 row decoder row decoder row decoder row decoder a0 a9 bs0 bs1 cs ras cas we
w9864g2db publication release date: january 27, 2003 - 7 - revision a1 7. functional description power up and initialization the default power up state of the mode regist er is unspecified. the following power up and initialization sequence need to be followed to guar antee the device being preconditioned to each user specific needs. during power up, all vdd and vdd q pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" st ate. the power up voltage must not exceed vdd +0.3v on any of the input pins or vdd supplie s. after power up, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional ei ght auto refresh cycles (cbr) are also required before or after programming the mode regist er to ensure proper subsequent operation. programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke mu st be high at least one cycle before the mode register set command can be issued. the mode r egister set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mode register set cycle and operation table. bank activate command the bank activate command must be applied befor e any read or write operation can be executed. the operation is similar to ras activate in ed o dram. the delay from when the bank activate command is applied to when the first read or writ e operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is det ermined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). read and write access modes after a bank has been activated, a read or write cycl e can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the a ccess and precharge operations between multiple banks, seamless data access operation among many di fferent pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
w9864g2db - 8 - burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of t he clock. the address inputs det ermine the starting column address for the burst. the mode register sets ty pe of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode regi ster set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. burst command the burst write command is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remain ing data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. read interrupted by a read a burst read may be interrupted by another read comm and. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read interrupted by a write to interrupt a burst read with a write comm and, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid dat a contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operat ion on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at l east one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from t he burst write cycle will be ignored. burst stop command a burst stop command may be used to terminate t he existing burst operati on but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other bur st length operations is illegal. the burst stop
w9864g2db publication release date: january 27, 2003 - 9 - revision a1 command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance st ate after a delay, which is equal to the cas latency in a burst read cycle, interrupted by burs t stop. if a burst stop command is issued during a full page burst write operation, then any residual dat a from the burst write cycle will be ignored. addressing sequence of sequential mode a column access is performed by increasing the addr ess from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2 . table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address bust length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
w9864g2db - 10 - auto-precharge command if a10 is set to high when the read or write comm and is issued, then the auto-precharge function is entered. during auto-precharge, a read command will ex ecute as normal with t he exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clo cks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. therefor e, use of a read, write, or precharge command is prohibited during a read or write cycle with auto-pr echarge. once the prechar ge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto- precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock del ay from the last burst write cy cle. this delay is referred to as write t dpl . the bank undergoing auto-precharge cannot be reactivated until t dpl and t rp are satisfied. this is referred to as t dal , data-in to active delay (t dal = t dpl + t rp ). when using the auto-precharge command, the interval between the bank acti vate command and the beginning of the internal precharge operation must satisfy t ras (min). precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0, and bs1 are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). self refresh command the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control si gnals, except cke, are disabled. the clock is internally disabled during se lf refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before t he next command can be issued. this delay is equal to the t ac cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in powe r down mode longer than the refresh period (t ref ) of the device.
w9864g2db publication release date: january 27, 2003 - 11 - revision a1 the power down mode is exited by bringing c ke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t ces (min.) + t ck (min.). no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state to prevent the sdram from regist ering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminat e a previous operation t hat is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same func tion as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don't cares. clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clo ck suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clo cked operation that was cu rrently being executed. there is a one clock delay between the registrati on of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bri nging cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited.
w9864g2db - 12 - table of operating modes fully synchronous operations are performed to latc h the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1), (2)) command device state cken-1 cken dqm bs0, 1 a10 a0-a9 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto-refresh idle h h x x x x l l l h self-refresh entry idle h l x x x x l l l h self refresh exit idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x h clock suspend mode exit active l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x h data write/output enable ac tive h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input leve l when commands are provided. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
w9864g2db publication release date: january 27, 2003 - 13 - revision a1 simplified state diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke s e l f s e l f e x i t c k e c k e w r i t e w i t h read write a u t o p r e c h a r g e a u t o p r e c h a r g e r ea d w i t h write w r i t e r e a d p r e ( pr ec har ge t er m i na t i on ) p r e ( p r ec ha r g e t er m i na t i o n) read b s t b s t pre manual input automatic sequence mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto precharge reada = read with auto precharge
w9864g2db - 14 - 8. dc characteristics absolute maximum rating parameter symbol rating unit notes input, column output voltage v in , v out -0.3 ? v dd +0.3 v 1 power supply voltage v dd, v ddq -0.3 ? 4.6 v 1 operating temperature t opr 0 ? 70 c 1 storage temperature t stg -55 ? 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those lis ted under absolute maximum ratings may adversely affect the life and reliability of the device. recommended dc operating conditions (t a = 0 to 70 c) parameter symbol min. typ. max. unit notes power supply voltage v dd 2.7 3.3 3.6 v 2 power supply voltage (for i/o buffer) v ddq 2.7 3.3 3.6 v 2 input high voltage v ih 2.0 - v dd +0.3 v 2 input low voltage v il -0.3 - 0.8 v 2 note: v ih (max.) = v dd /v ddq +1.2v for pulse width < 5 ns v il (min.) = v ss /v ssq -1.2v for pulse width < 5 ns capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 to a10, bs0, bs1, cs , ras , cas , we , dqm, cke) c i 2.5 4 pf input capacitance (clk) c clk 2.5 4 pf input/output capacitance (dq0 ? dq31) c o 4 6.5 pf note: these parameters are periodically sampled and not 100% tested
w9864g2db publication release date: january 27, 2003 - 15 - revision a1 dc characteristics (v dd = 3.6v ? 2.7v, t a = 0 ? 70 c) -7 parameter symbol max. unit notes operating current tck = min., trc = min. active precharge command cycling without burst operation 1 bank operation i cc1 80 3 standby current tck = min., cs = v ih v ih /l = v ih (min.)/vil (max.) cke = v ih i cc2 30 3 bank: inactive state cke = v il (power down mode) i cc2p 1 3 standby current clk = v il , cs = v ih v ih /l =v ih (min.)/v il (max.) cke = v ih i cc2s 8 bank: inactive state cke = v il (power down mode) i cc2ps 1 no operating current tck = min., cs = v ih (min.) cke = v ih i cc3 55 bank: active state (4 banks) cke = v il (power down mode) i cc3p 5 burst operating current (tck = min.) read/write command cycling i cc4 145 3, 4 auto refresh current (tck = min.) auto refresh command cycling i cc5 110 ma 3 i cc6 1 ma self refresh current (cke = 0.2v) self refresh mode i cc6l 400 a parameter symbol min. max. unit notes input leakage current (0v v in v dd , all other pins not under test = 0v) i i (l) -5 5 a output leakage current (output disable, 0v v out v ddq ) v o (l) -5 5 a lvttl output "h" level voltage (i out = -2 ma) v oh 2.4 - v lvttl output "l" level voltage (i out = 2 ma) v ol - 0.4 v
w9864g2db - 16 - 9. ac characteristics (v dd = 3.6v ~2.7v, v ss = 0v, t a = 0 to 70 c) (notes: 5, 6.) -7 parameter symbol min. max. unit ref/active to ref/active command period trc 65 active to precharge command period tras 45 100000 active to read/write command delay time trcd 20 ns read/write(a) to read/write(b)command period tccd 1 cycle precharge to active(b) command period trp 20 active(a) to active(b) command period trrd 14 8 write recovery time cl* = 2 cl* = 3 twr 7 8 1000 clk cycle time cl* = 2 cl* = 3 tck 7 1000 clk high level tch 2 clk low level tcl 2 access time from clk cl* = 2 tac 6 cl* = 3 5.5 output data hold time toh 3 output data high impedance time thz 3 7 output data low impedance time tlz 0 power down mode entry time tsb 0 7 transition time of clk (rise and fall) tt 0.5 10 data-in-set-up time tds 1.5 data-in hold time tdh 1 address set-up time tas 1.5 address hold time tah 1 cke set-up time tcks 1.5 cke hold time tckh 1 command set-up time tcms 1.5 command hold time tcmh 1 ns refresh time tref 64 ms mode register set cycle time trsc 14 ns
w9864g2db publication release date: january 27, 2003 - 17 - revision a1 notes: 1. operation exceeds "absolute maximum rating" may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycle rate and listed va lues are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading condi tions. specified values are obtained with output open. 5. power up sequence (1) power up must be performed in the following sequence. (2) power must be applied to v dd and v ddq (simultaneously) while all input signals are held in the ?nop? state. the clk signals must be started at the same time. (3) after power-up a pause of at least 200 seconds is r equired. it is required that dqm and cke signals then be held ? high? (v dd levels) to ensure that the dq output is impedance. (4) all banks must be precharged. (5) the mode register set command must be asserted to initialize the mode register. (6) a minimum of eight auto refresh dummy cycles is required to stabilize the internal circuitry of the device. 6. ac testing conditions parameter conditions output reference level 1.4v output load see diagram below input signal levels (v ih /v il ) 2.4v/0.4v transition time (rise and fall) of input signal 1 ns input reference level 1.4v 50 ohms 1.4 v ac test load z = 50 ohms output 50pf 1. transition times are measured between v ih and v il . 2. t hz defines the time at which the outputs achieve the open cir cuit condition and is not referenced to output level. 3. these parameters account for the number of clock cycle s and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1) t ch is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min.). t cl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max.).
w9864g2db - 18 - (2) a.c latency characteristics cke to clock disable (cke latency) 1 cycle dqm to output to hi-z (read dqm latency) 2 dqm to output to hi-z (write dqm latency) 0 write command to input data (write data latency) 0 cs to command input ( cs latency) 0 cl = 2 2 precharge to dq hi-z lead time cl = 3 3 cl = 2 1 precharge to last valid data out cl = 3 2 cl = 2 2 bust stop command to dq hi-z lead time cl = 3 3 cl = 2 1 bust stop command to last valid data out cl = 3 2 cl = 2 bl + t rp cycle + ns read with auto-precharge command to active/ref command cl = 3 bl + t rp cl = 2 bl + t rp write with auto-precharge command to active/ref command cl = 3 bl + t rp
w9864g2db publication release date: january 27, 2003 - 19 - revision a1 10. timing waveforms command input timing t c k clk a0-a10 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah
w9864g2db - 20 - timing waveforms, continued read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a10 bs0, 1 dq valid data-out valid data-out
w9864g2db publication release date: january 27, 2003 - 21 - revision a1 timing waveforms, continued control timing of input data *dqm2,3="l" clk (word mask) t cmh t cms t cmh t cms dqm0 t cms t cmh t cmh dqm1 dq0 -dq7 dq16 -dq23 dq8-dq15 dq24-dq31 t dh t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh valid data-in valid data-in t dh valid data-in t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t dh t dh t ds t ds t ds t ds dq0 -dq7 clk cke t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in dq24 -dq31 dq16 -dq23 dq8 -dq15 (clock mask) t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t ds t ds valid data-in valid data-in valid data-in t cms
w9864g2db - 22 - timing waveforms, continued control timing of output data dq0 -dq7 valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t hz t lz t ac t oh t ac open clk (output enable) dqm0 t cmh t cms t cmh t cms t cmh t cms t cmh t cms dqm1 t oh t ac t ac t hz t ac t ac valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh dq8 -dq15 t ac t hz t lz open dq24 -dq31 dq16 -dq23 valid data-out valid data-out t oh t ac t oh t ac t oh t hz t ac t oh t ac t oh valid data-out valid data-out t oh t oh t lz t oh valid data-out valid data-out valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq16 -dq23 t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq24 -dq31 t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq0 -dq7 cke clk t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq8 -dq15 (clock mask) *dqm2,3="l"
w9864g2db publication release date: january 27, 2003 - 23 - revision a1 timing waveforms, continued mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 bs0 a0 a11 a0 bs1 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a10 bs0,1 register set data next command a0 reserved "0" "0" "0" "0"
w9864g2db - 24 - 11. operating timing example interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3 ras cas bs1 bs0
w9864g2db publication release date: january 27, 2003 - 25 - revision a1 operating timing example, continued interleaved bank read (burst length = 4, cas latency = 3, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb ap* t rcd
w9864g2db - 26 - operating timing example, continued interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0
w9864g2db publication release date: january 27, 2003 - 27 - revision a1 operating timing example, continued interleaved bank read (burst length = 8, cas latency = 3, autoprecharge) a0-a9 bank #0 idle bank #1 bank #2 bank #3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0
w9864g2db - 28 - operating timing example, continued interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9 a10 bs1 we cas ras cs idle bank #0 bank #1 bank #2 bank #3 bs0 ax4 ax5 ax6 ax7 by0 by1 by2 by3
w9864g2db publication release date: january 27, 2003 - 29 - revision a1 operating timing example, continued interleaved bank write (burst length = 8, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap* bs0
w9864g2db - 30 - operating timing example, continued page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t ras t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap* bs0
w9864g2db publication release date: january 27, 2003 - 31 - revision a1 operating timing example, continued page mode read/write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 qq q q q q dd d d d (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0
w9864g2db - 32 - operating timing example, continued autoprecharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs bs1 t rc t ras t rp t ras t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 bs0 bx0 bx2 bx1 bx3
w9864g2db publication release date: january 27, 2003 - 33 - revision a1 operating timing example, continued autoprecharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs bs1 t rc t rc t rp t ras t rp raa t rcd t rcd rab rac raa rab cax rac bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ras bs0 caw aw0 aw1 aw2 aw3
w9864g2db - 34 - operating timing example, continued autorefresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9 a10 we cas ras cs bs0,1
w9864g2db publication release date: january 27, 2003 - 35 - revision a1 operating timing example, continued self-refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t rc no operation cycle
w9864g2db - 36 - operating timing example, continued bust read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk (clk = 100 mhz) qq q q d d dqqqq read read single write active bank #0 idle bank #1 bank #2 bank #3 cs ras cas we bs1 a10 a0-a9 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 t ac t ac bs0
w9864g2db publication release date: january 27, 2003 - 37 - revision a1 operating timing example, continued power-down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a10 bs we cas ras cs read
w9864g2db - 38 - operating timing example, continued auto-precharge timing (write cycle) d0 write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act ap act ap act d1 d0 ap act d1 d2 d3 ap act d0 d1 d2 d3 d4 d5 d6 d7 write write write write write write write d0 (1) cas latency=2 (2) cas latency=3 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras (min.) represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w9864g2db publication release date: january 27, 2003 - 39 - revision a1 operating timing example, continued auto-precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w9864g2db - 40 - operating timing example, continued timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict. read write 11 10 9 8 7 6 5 4 3 2 1 read read read write write d0 d1 d2 d3 write dq dq ( a ) command 0 dq dq dqm ( b ) command dqm ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 (1) cas latency=2 ( a ) command (2) cas latency=3 in the case of burst length = 4
w9864g2db publication release date: january 27, 2003 - 41 - revision a1 operating timing example, continued timing chart of write to read cycle 0 11 10 9 8 7 6 5 4 3 2 1 in the case of burst length = 4 q0 read q1 q2 q3 read write write d0 d1 dq dq ( a ) command ( b ) command dqm dqm (2) cas latency = 3 q0 q1 q2 q3 d0 read write read write q0 q1 q2 q3 q0 q1 q2 q3 ( a ) command dq dq dqm ( b ) command dqm (1) cas latency = 2 d0 d0 d1
w9864g2db - 42 - operating timing example, continued timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq dq q0 q1 q2 q3 q0 q1 q2 q3 read bst ( a ) cas latency =2 command ( b ) cas latency = 3 command (3) read cycle q4 q4 dq d0 d1 d2 d3 write bst command (2) write cycle d4 note: represents the burst stop command bst
w9864g2db publication release date: january 27, 2003 - 43 - revision a1 operating timing example, continued timing chart of burst stop cycle (precharge command) in the case of burst lenght = 8 note: represents the precharge command prcg read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 read prcg q4 q4 ( a )cas latency =2 ( b )cas latency = 3 dq dq (1) read cycle (2) write cycle commad commad write prcg d0 d1 d2 d3 d0 d1 d2 d3 write prcg d4 d4 ( b ) cas latency = 3 dq ( a ) cas latency =2 dqm dqm dq t wr t wr commad commad
w9864g2db - 44 - operating timing example, continued cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w9864g2db publication release date: january 27, 2003 - 45 - revision a1 operating timing example, continued cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk
w9864g2db - 46 - operating timing example, continued self refresh/power down mode exit timing asynchronous control input buffer turn on time (power down mode exit time) is specified by t cks (min.) + t ck (min.) command nop clk cke command a ) t ck < t cks (min.) + t ck (min.) input buffer enable command clk cke command b) t ck >= t cks (min.) + t ck (min.) input buffer enable note: command nop all input buffer (include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command t ck t ck t cks (min)+t ck (min) t cks (min)+t ck (min)
w9864g2db publication release date: january 27, 2003 - 47 - revision a1 12. package dimensions tfbga 90 balls pitch = 0.8 mm 0.53 0.4 0.80 0.26
w9864g2db - 48 - 13. version history version date page description a1 january 27, 2003 - formal version headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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